Core peripherals PM0214
206/262 PM0214 Rev 9
4.2.10 MPU register map
Table 44. MPU register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
MPU_TYPER
Reserved IREGION[7:0] DREGION[7:0] Reserved
SEPARATE
Reset Value 00000000000000000001000000000000
0x04
MPU_CTRL
Reserved
PRIVDEFENA
HFNMIENA
ENABLE
Reset Value 00000000000000000000000000000000
0x08
MPU_RNR
Reserved
REGION[7:0]
Reset Value 00000000000000000000000000000000
0x0C
MPU_RBAR
ADDR[31:N]...
VALID
REGION[3:0]
Reset Value 00000000000000000000000000000000
0x10
MPU_RASR
Reserved
XN
Reserved
AP[2:0]
Reserved
TEX[2:0]
S C B SRD[7:0]
Reserved
SIZE
EN ABLE
Reset Value 00000000000000000000000000000000
0x14
MPU_RBAR_A1
(1)
ADDR[31:N]...
VALID
REGION[3:0]
Reset Value 00000000000000000000000000000000
0x18
MPU_RASR_A1
(2)
Reserved
XN
Reserved
AP[2:0]
Reserved
TEX[2:0]
S C B SRD[7:0]
Reserved
SIZE
EN ABLE
Reset Value 00000000000000000000000000000000
0x1C
MPU_RBAR_A2
(1)
ADDR[31:N]...
VALID
REGION[3:0]
Reset Value 00000000000000000000000000000000
0x20
MPU_RASR_A2
(2)
Reserved
XN
Reserved
AP[2:0]
Reserved
TEX[2:0]
S C B SRD[7:0]
Reserved
SIZE
EN ABLE
Reset Value 00000000000000000000000000000000