PM0214 Rev 9 243/262
PM0214 Core peripherals
261
4.4.17 Auxiliary fault status register (AFSR)
Address offset: 0x3C
Reset value: undefined
Required privilege: Privileged
4.4.18 System control block design hints and tips
Ensure software uses aligned accesses of the correct size to access the system control
block registers:
• except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler. to determine the true faulting address:
1. Read and save the MMFAR or BFAR value.
2. Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The
MMFAR or BFAR address is valid only if this bit is 1.
Software must follow this sequence because another higher priority exception might change
the MMFAR or BFAR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMFAR or BFAR value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMPDEF[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
IMPDEF[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 IMPDEF: Implementation defined. The AFSR contains additional system fault information. The
bits map to the AUXFAULT input signals.
This register is read, write to clear. This means that bits in the register read normally, but
writing 1 to any bit clears that bit to 0.
Each AFSR bit maps directly to an AUXFAULT input of the processor, and a single-cycle HIGH
signal on the input sets the corresponding AFSR bit to one. It remains set to 1 until you write 1
to the bit to clear it to zero.
When an AFSR bit is latched as one, an exception does not occur. Use an interrupt if an
exception is required.
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