Core peripherals PM0214
202/262 PM0214 Rev 9
4.2.7 MPU region number register (MPU_RNR)
Address offset: 0x08
Reset value: 0x0000 0000
Required privilege: Privileged
The MPU_RNR register selects which memory region is referenced by the MPU_RBAR and
MPU_RASR registers.
Bits 31:3 Reserved, forced by hardware to 0.
Bit 2 PRIVDEFENA: Enable priviliged software access to default memory map.
0: If the MPU is enabled, disables use of the default memory map. Any memory access to a
location not covered by any enabled region causes a fault.
1: If the MPU is enabled, enables use of the default memory map as a background region for
privileged software accesses.
Note: When enabled, the background region acts as if it is region number -1. Any region that
is defined and enabled has priority over this default map.
If the MPU is disabled, the processor ignores this bit.
Bit 1 HFNMIENA: Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the
value of the ENABLE bit
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
Note: When the MPU is disabled, if this bit is set to 1 the behavior is unpredictable.
Bit 0 ENABLE: Enables the MPU
0: MPU disabled
1: MPU enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved REGION[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, forced by hardware to 0.
Bits 7:0 REGION[7:0]: MPU region
These bits indicate the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, you write the required region number to this register before accessing the
MPU_RBAR or MPU_RASR. However you can change the region number by writing to the
MPU_RBAR register with the VALID bit set to 1, see MPU region base address register
(MPU_RBAR). This write updates the value of the REGION field.
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