Revision history PM0214
260/262 PM0214 Rev 9
5 Revision history
Table 58. Document revision history
Date Revision Changes
20-Feb-2012 1 Initial release.
09-Jul-2012 2
Changed reset value in Section 4.6.2: Floating-point context control
register (FPCCR).
Added Table 1: Applicable products.
04-Sep-2012 3
Added information on the STM32F3xxx Cortex-M4 processor.
Added extra part numbers to Table 1: Applicable products.
Added related documentation references to Introduction.
Changed “IEEE754-compliant single-precision FPU” bullet in
Section 1.3.3: Cortex-M4 processor features and benefits summary.
Added information on extended interrupt/event controller to
Section 2.5.3: External event input / extended interrupt and event
input.
Changed first “interrupt” bullet in Section 4.3: Nested vectored
interrupt controller (NVIC).
Removed outdated reset value information in Section 4.4.7:
Configuration and control register (CCR), and for 0x14 offset in
Table 52: System fault handler priority fields.
Added a note about IEEE 754 to Section 4.6: Floating point unit
(FPU).
12-May-2014 4
Updated Reference documents.
Updated Section 4.4.1: Auxiliary control register (ACTLR).
Updated Section 4.5.1: SysTick control and status register
(STK_CTRL).
18-Apr-2016 5
Updated:
– Introduction
– Reference documents
– Section 2.5.3: External event input / extended interrupt and event
input
– Section 4.6.7: Enabling and clearing FPU exception interrupts
– Table 51: Priority grouping
Removed:
– Table 1: Applicable products
02-Oct-2017 6
Updated document scope to include STM32L4+ Series impacting
only the document’s title and cover page.
Updated Table 49: NVIC register map and reset values
21-Feb-2019 7
Updated:
– Document scope to include STM32MP1 Series, STM32WB Series,
STM32G4 Series
– Title and cover page
– Section 1: About this document
– General update of Section 4.3: Nested vectored interrupt controller
(NVIC)
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