ST STM32H7 Series User Manual

The Cortex-M4 processor PM0214
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2.5.1 Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wakeup events, for example a debug operation that
wakes up the processor. Therefore software must be able to put the processor back into
sleep mode after such an event. A program might have an idle loop to put the processor
back to sleep mode.
Wait for interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode (unless the
wake-up condition is true, as shown in Wakeup from WFI or sleep-on-exit on page 48).
When the processor executes a WFI instruction, it stops executing instructions and enters
sleep mode. See WFI on page 192 for more information.
Wait for event
The wait for event instruction, WFE, causes entry to sleep mode depending on the value of
a one-bit event register. When the processor executes a WFE instruction, it checks the
value of the event register:
• 0: the processor stops executing instructions and enters sleep mode
• 1: the processor clears the register to 0 and continues executing instructions without
entering sleep mode.
See WFE on page 191 for more information.
If the event register is 1, this indicates that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because an external event signal is
asserted, or a processor in the system has executed an SEV instruction, as shown in SEV
on page 189. Software cannot access this register directly.
Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution
of an exception handler, it returns to Thread mode and immediately enters sleep mode. Use
this mechanism in applications that only require the processor to run when an exception
occurs.
2.5.2 Wakeup from sleep mode
The conditions for the processor to wakeup depend on the mechanism that caused it to
enter sleep mode.
Wakeup from WFI or sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to
cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit
to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher
priority than current exception priority, the processor wakes up but does not execute the
interrupt handler until the processor sets PRIMASK to zero. For more information about
PRIMASK and FAULTMASK see Exception mask registers on page 23.

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English

Summary

About this document

Typographical Conventions

Defines formatting used in the document for clarity.

List of Abbreviations for Registers

Provides a list of abbreviations used in register descriptions for quick reference.

STM32 Cortex-M4 Processor Overview

Introduces the STM32 Cortex-M4 processor's architecture and key features.

The Cortex-M4 Processor

Programmer's Model

Describes registers, modes, and privilege levels for software execution.

Memory Model

Details the processor's memory map, access behavior, and bit-banding features.

Exception Model

Explains exception states, types, priorities, and handling mechanisms.

Fault Handling

Covers fault types, escalation, status registers, and lockup conditions.

Power Management

Describes mechanisms for entering and exiting low-power sleep modes.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary

Lists supported Cortex-M4 instructions and their organization.

Memory Access Instructions

Details instructions for loading and storing data from/to memory.

General Data Processing Instructions

Explains instructions for arithmetic, logical, and data manipulation.

Multiply and Divide Instructions

Describes instructions for multiplication and division operations.

Floating-Point Instructions

Details instructions for FPU operations, including VFPv4-SP extension.

Miscellaneous Instructions

Covers instructions like breakpoints, barriers, and supervisor calls.

Core Peripherals

About the STM32 Cortex-M4 Core Peripherals

Introduces the core peripherals accessible via the Private Peripheral Bus (PPB).

Memory Protection Unit (MPU)

Explains the MPU for memory region definition and access control.

Nested Vectored Interrupt Controller (NVIC)

Describes the NVIC for managing interrupts and exceptions with priority levels.

System Control Block (SCB)

Details registers for system control, configuration, and exception reporting.

SysTick Timer (STK)

Explains the 24-bit SysTick timer for system timing and RTOS ticks.

Floating Point Unit (FPU)

Describes the FPU for single-precision floating-point operations.

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