Core peripherals PM0214
200/262 PM0214 Rev 9
4.2.5 MPU type register (MPU_TYPER)
Address offset: 0x00
Reset value: 0x0000 0800
Required privilege: Privileged
The MPU_TYPER register indicates whether the MPU is present, and if so, how many
regions it supports.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved IREGION[7:0]
rrrrrrrr
1514131211109876543210
DREGION[7:0] Reserved
SEPA
RATE
rrrrrr r r
Bits 31:24 Reserved.
Bits 23:16 IREGION[7:0]: Number of MPU instruction regions.
These bits indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION
field.
Bits 15:8 DREGION[7:0]: Number of MPU data regions.
These bits indicates the number of supported MPU data regions.
0x08: Eight MPU regions
0x00: MPU not present
Bits 7:1 Reserved.
Bit 0 SEPARATE: Separate flag.
This bit indicates support for unified or separate instruction and data memory maps:
0 = Unified
1 = Separate
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