The STM32 Cortex-M4 instruction set PM0214
124/262 PM0214 Rev 9
Restrictions
In these instructions:
• Do not use either SP or PC
• RdHi and RdLo must be different registers.
Condition flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
3.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
Where:
• ‘cond’ is an optional condition code (see Conditional execution on page 65).
• ‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn.
• ‘Rn,’ is the register holding the value to be divided.
• ‘Rm’ is a register holding the divisor.
Operation
SDIV performs a signed integer division of the value in
Rn
by the value in
Rm
.
UDIV performs an unsigned integer division of the value in
Rn
by the value in
Rm
.
For both instructions, if the value in
Rn
is not divisible by the value in
Rm
, the result is
rounded towards zero.
Restrictions
Do not use either SP or PC
.
Condition flags
These instructions do not change the flags.
Examples
SDIV R0, R2, R4; signed divide, R0 = R2/R4
UDIV R8, R8, R1; unsigned divide, R8 = R8/R1
To Next Page
Loading...
Need help?
General
