Core peripherals PM0214
212/262 PM0214 Rev 9
4.3.4 Interrupt set-pending register x (NVIC_ISPRx)
Address offset: 0x200 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_ISPR0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_ISPR1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_ISPR6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_ISPR7 bits 0 to 15 are for interrupt 224 to 239, respectively
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND[31:16]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
1514131211109876543210
SETPEND[15:0]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
Bits 31:0 SETPEND: Interrupt set-pending bits
Write:
0: No effect
1: Changes interrupt state to pending
Read:
0: Interrupt is not pending
1: Interrupt is pending
Writing 1 to the ISPR bit corresponding to an interrupt that is pending has no effect.
Writing 1 to the ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to
pending.
Bits 16 to 31 of the NVIC_ISPR7 register are reserved.
To Next Page
Loading...
Need help?
General
