PM0214 Rev 9 199/262
PM0214 Core peripherals
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4.2.4 MPU design hints and tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a
region that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
• Except for the RASR, it must use aligned word accesses
• For the RASR it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable
unused regions to prevent any previous region settings from affecting the new MPU setup.
Recommended MPU configuration
The STM32 microcontroller system has only a single processor, so you should program the
MPU as follows:
In STM32 implementations, the shareability and cache policy attributes do not affect the
system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
Note: The MPU attributes don't affect DMA data accesses to the memory/peripherals address
spaces. therefore, in order to protect the memory areas against inadvertent DMA accesses,
the MPU must control the SW/CPU access to the DMA registers.
Table 42. Memory region attributes for STM32
Memory region TEX C B S Memory type and attributes
Flash memory b000 1 0 0 Normal memory, Non-shareable, write-through
Internal SRAM b000 1 0 1 Normal memory, Shareable, write-through
External SRAM b000 1 1 1 Normal memory, Shareable, write-back, write-allocate
Peripherals b000 0 1 1 Device memory, Shareable
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