ST STM32H7 Series User Manual

PM0214 Rev 9 233/262
PM0214 Core peripherals
261
4.4.8 System handler priority registers (SHPRx)
The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that
have configurable priority.
SHPR1-SHPR3 are byte accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,
and bits[3:0] read as zero and ignore writes (where M=4).
System handler priority register 1 (SHPR1)
Address offset: 0x18
Reset value: 0x0000 0000
Required privilege: Privileged
System handler priority register 2 (SHPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
Required privilege: Privileged
Table 52. System fault handler priority fields
Handler Field Register description
Memory management fault PRI_4
System handler priority register 1 (SHPR1)Bus fault PRI_5
Usage fault PRI_6
SVCall PRI_11
System handler priority register 2 (SHPR2) on
page 233
PendSV PRI_14
System handler priority register 3 (SHPR3) on
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SysTick PRI_15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PRI_6[7:4] PRI_6[3:0]
rw rw rw rw r r r r
1514131211109876543210
PRI_5[7:4] PRI_5[3:0] PRI_4[7:4] PRI_4[7:4]
rw rw rw rw r r r r rw rw rw rw r r r r
Bits 31:24 Reserved, must be kept cleared
Bits 23:16
PRI_6: Priority of system handler 6, usage fault
Bits 15:8
PRI_5: Priority of system handler 5, bus fault
Bits 7:0
PRI_4: Priority of system handler 4, memory management fault

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English