The STM32 Cortex-M4 instruction set PM0214
120/262 PM0214 Rev 9
SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
3.6.8 SMMUL
Signed most significant word multiply
Syntax
op{R}{cond} Rd, Rn, Rm
Where:
• op is one of the following:
SMMUL: Signed most significant word multiply.
R: a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before the high
word is extracted.
• ‘cond’ is an optional condition code (see Conditional execution on page 65).
• ‘Rd’ is the destination register.
• ‘Rn’, ‘Rm’ are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit
signed integers. The SMMUL instruction:
1. Multiplies the values from Rn and Rm.
2. Optionally rounds the result, otherwise truncates the result.
3. Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction: Do not use either SP or PC.
Condition flags
This instruction does not affect the condition code flags.
Examples
SMULL R0, R4, R5 ; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0
SMULLR R6, R2 ; Multiplies R6 and R2, rounds the top 32 bits
; and writes to R6.