ST STM32H7 Series User Manual

PM0214 Rev 9 193/262
PM0214 Core peripherals
261
4 Core peripherals
4.1 About the STM32 Cortex-M4 core peripherals
The address map of the Private peripheral bus (PPB) is:
In register descriptions,
• Register type is described as follows:
– RW: Read and write.
– RO: Read-only.
– WO: Write-only.
• Required privilege gives the privilege level required to access the register, as follows:
– Privileged: Only privileged software can access the register.
– Unprivileged: Both unprivileged and privileged software can access the register.
4.2 Memory protection unit (MPU)
This section describes the Memory protection unit (MPU) which is implemented in some
STM32 microcontrollers. Refer to the corresponding device datasheet to see if the MPU is
present in the STM32 type you are using.
The MPU divides the memory map into a number of regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
• Independent attribute settings for each region
• Overlapping regions
• Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-
M4 MPU defines:
• Eight separate memory regions, 0-7
• A background region.
Table 37. STM32 core peripheral register regions
Address Core peripheral Description
0xE000E010-0xE000E01F System timer Table 55 on page 251
0xE000E100-0xE000E4EF
Nested vectored interrupt
controller
Table 49 on page 219
0xE000ED00-0xE000ED3F System control block Table 53 on page 244
0xE000ED88-0xE000ED8B
Floating point unit
coprocessor access control
Table 56 on page 252
0xE000ED90-0xE000EDB8 Memory protection unit Table 44 on page 206
0xE000EF00-0xE000EF03
Nested vectored interrupt
controller
Table 49 on page 219
0xE000EF30-0xE000EF44 Floating point unit Table 56 on page 252

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English