ST STM32H7 Series User Manual

PM0214 Rev 9 213/262
PM0214 Core peripherals
261
4.3.5 Interrupt clear-pending register x (NVIC_ICPRx)
Address offset: 0x280 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_ICPR0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_ICPR1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_ICPR6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_ICPR7 bits 0 to 15 are for interrupt 224 to 239, respectively
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND[31:16]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109876543210
CLRPEND[15:0]
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:0 CLRPEND: Interrupt clear-pending bits
Write:
0: No effect
1: Removes the pending state of an interrupt
Read:
0: Interrupt is not pending
1: Interrupt is pending
Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
Bits 16 to 31 of the NVIC_ICPR7 register are reserved.

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English