PM0214 Rev 9 117/262
PM0214 The STM32 Cortex-M4 instruction set
261
3.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
Where:
• op is one of:
SMLSD: Signed multiply subtract dual.
SMLSDX: Signed multiply subtract dual reversed
SMLSLD: Signed multiply subtract long dual.
SMLSLDX: Signed multiply subtract long dual reversed.
– If X is present, the multiplications are bottom × top and top × bottom.
– If the X is omitted, the multiplications are bottom × bottom and top × top.
• ‘cond’ is an optional condition code (see Conditional execution on page 65)
• ‘Rd’ is the destination register.
• ‘Rn’, ‘Rm’ are registers holding the first and second operands
• ‘Ra’ is the register holding the accumulate value
Operation
The SMLSD instruction interprets the values from the first and second operands as four
signed halfwords. This instruction:
1. Optionally rotates the halfwords of the second operand.
2. Performs two signed 16 × 16-bit halfword multiplications.
3. Subtracts the result of the upper halfword multiplication from the result of the lower
halfword multiplication.
4. Adds the signed accumulate value to the result of the subtraction.
5. Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords.
This instruction:
1. Optionally rotates the halfwords of the second operand.
2. Performs two signed 16 × 16-bit halfword multiplications.
3. Subtracts the result of the upper halfword multiplication from the result of the lower
halfword multiplication.
4. Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
5. Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions: Do not use either SP or PC.
Condition flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur
during the multiplications or subtraction.
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