Core peripherals PM0214
210/262 PM0214 Rev 9
4.3.2 Interrupt set-enable register x (NVIC_ISERx)
Address offset: 0x100 + 0x04 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Required privilege: Privileged
NVIC_ISER0 bits 0 to 31 are for interrupt 0 to 31, respectively
NVIC_ISER1 bits 0 to 31 are for interrupt 32 to 63, respectively
....
NVIC_ISER6 bits 0 to 31 are for interrupt 192 to 223, respectively
NVIC_ISER7 bits 0 to 15 are for interrupt 224 to 239, respectively
Note: The number of interrupts is product-dependent. Refer to reference manual/datasheet of
relevant STM32 product for related information.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA[31:16]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
1514131211109876543210
SETENA[15:0]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
Bits 31:0 SETENA: Interrupt set-enable bits.
Write:
0: No effect
1: Enable interrupt
Read:
0: Interrupt disabled
1: Interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending,
but the NVIC never activates the interrupt, regardless of its priority.
Bits 16 to 31 of the NVIC_ISER7 register are reserved.
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