ST STM32H7 Series User Manual

The STM32 Cortex-M4 instruction set PM0214
160/262 PM0214 Rev 9
3.10.10 VLDM
Floating-point Load Multiple
Syntax
VLDM{mode}{cond}{.size} Rn{!}, list
Where:
• ‘mode’ is the addressing mode:
IA: Increment After. The consecutive addresses start at the address specified in Rn.
DB: Decrement Before. The consecutive addresses end just before the address
specified in Rn.
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Size’ is an optional data size specifier.
• ‘Rn’ is the base register. The SP can be used
• ‘!’ is the command to the instruction to write a modified value back to Rn. This is
required if mode == DB, and is optional if mode == IA.
• ‘list’ is the list of extension registers to be loaded, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and surrounded by
brackets.
Operation
This instruction loads multiple extension registers from consecutive memory locations using
an address from an Arm core register as the base address.
Restrictions
The restrictions are:
• If size is present, it must be equal to the size in bits, 32 or 64, of the registers in list.
• For the base address, the SP can be used.
• In the Arm instruction set, if ! is not specified the PC can be used.
• list must contain at least one register. If it contains doubleword registers, it must not
contain more than 16 registers.
• If using the Decrement Before addressing mode, the write back flag, !, must be
appended to the base register specification.
Condition flags
These instructions do not change the flags.

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English

Summary

About this document

Typographical Conventions

Defines formatting used in the document for clarity.

List of Abbreviations for Registers

Provides a list of abbreviations used in register descriptions for quick reference.

STM32 Cortex-M4 Processor Overview

Introduces the STM32 Cortex-M4 processor's architecture and key features.

The Cortex-M4 Processor

Programmer's Model

Describes registers, modes, and privilege levels for software execution.

Memory Model

Details the processor's memory map, access behavior, and bit-banding features.

Exception Model

Explains exception states, types, priorities, and handling mechanisms.

Fault Handling

Covers fault types, escalation, status registers, and lockup conditions.

Power Management

Describes mechanisms for entering and exiting low-power sleep modes.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary

Lists supported Cortex-M4 instructions and their organization.

Memory Access Instructions

Details instructions for loading and storing data from/to memory.

General Data Processing Instructions

Explains instructions for arithmetic, logical, and data manipulation.

Multiply and Divide Instructions

Describes instructions for multiplication and division operations.

Floating-Point Instructions

Details instructions for FPU operations, including VFPv4-SP extension.

Miscellaneous Instructions

Covers instructions like breakpoints, barriers, and supervisor calls.

Core Peripherals

About the STM32 Cortex-M4 Core Peripherals

Introduces the core peripherals accessible via the Private Peripheral Bus (PPB).

Memory Protection Unit (MPU)

Explains the MPU for memory region definition and access control.

Nested Vectored Interrupt Controller (NVIC)

Describes the NVIC for managing interrupts and exceptions with priority levels.

System Control Block (SCB)

Details registers for system control, configuration, and exception reporting.

SysTick Timer (STK)

Explains the 24-bit SysTick timer for system timing and RTOS ticks.

Floating Point Unit (FPU)

Describes the FPU for single-precision floating-point operations.

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