The STM32 Cortex-M4 instruction set PM0214
160/262 PM0214 Rev 9
3.10.10 VLDM
Floating-point Load Multiple
Syntax
VLDM{mode}{cond}{.size} Rn{!}, list
Where:
• ‘mode’ is the addressing mode:
IA: Increment After. The consecutive addresses start at the address specified in Rn.
DB: Decrement Before. The consecutive addresses end just before the address
specified in Rn.
• ‘cond’ is an optional condition code, see Conditional execution on page 65.
• ‘Size’ is an optional data size specifier.
• ‘Rn’ is the base register. The SP can be used
• ‘!’ is the command to the instruction to write a modified value back to Rn. This is
required if mode == DB, and is optional if mode == IA.
• ‘list’ is the list of extension registers to be loaded, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and surrounded by
brackets.
Operation
This instruction loads multiple extension registers from consecutive memory locations using
an address from an Arm core register as the base address.
Restrictions
The restrictions are:
• If size is present, it must be equal to the size in bits, 32 or 64, of the registers in list.
• For the base address, the SP can be used.
• In the Arm instruction set, if ! is not specified the PC can be used.
• list must contain at least one register. If it contains doubleword registers, it must not
contain more than 16 registers.
• If using the Decrement Before addressing mode, the write back flag, !, must be
appended to the base register specification.
Condition flags
These instructions do not change the flags.
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