ST STM32H7 Series User Manual

PM0214 Rev 9 7/262
PM0214 Contents
8
4.2.9 MPU region attribute and size register (MPU_RASR) . . . . . . . . . . . . . 204
4.2.10 MPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
4.3 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 208
4.3.1 Accessing the Cortex-M4 NVIC registers using CMSIS . . . . . . . . . . . 209
4.3.2 Interrupt set-enable register x (NVIC_ISERx) . . . . . . . . . . . . . . . . . . . 210
4.3.3 Interrupt clear-enable register x (NVIC_ICERx) . . . . . . . . . . . . . . . . . 211
4.3.4 Interrupt set-pending register x (NVIC_ISPRx) . . . . . . . . . . . . . . . . . . 212
4.3.5 Interrupt clear-pending register x (NVIC_ICPRx) . . . . . . . . . . . . . . . . 213
4.3.6 Interrupt active bit register x (NVIC_IABRx) . . . . . . . . . . . . . . . . . . . . 214
4.3.7 Interrupt priority register x (NVIC_IPRx) . . . . . . . . . . . . . . . . . . . . . . . 215
4.3.8 Software trigger interrupt register (NVIC_STIR) . . . . . . . . . . . . . . . . . 216
4.3.9 Level-sensitive and pulse interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 217
4.3.10 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
4.3.11 NVIC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
4.4 System control block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.4.1 Auxiliary control register (ACTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
4.4.2 CPUID base register (CPUID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
4.4.3 Interrupt control and state register (ICSR) . . . . . . . . . . . . . . . . . . . . . . 225
4.4.4 Vector table offset register (VTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
4.4.5 Application interrupt and reset control register (AIRCR) . . . . . . . . . . . 228
4.4.6 System control register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
4.4.7 Configuration and control register (CCR) . . . . . . . . . . . . . . . . . . . . . . 231
4.4.8 System handler priority registers (SHPRx) . . . . . . . . . . . . . . . . . . . . . 233
4.4.9 System handler control and state register (SHCSR) . . . . . . . . . . . . . . 235
4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR) . . . 237
4.4.11 Usage fault status register (UFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
4.4.12 Bus fault status register (BFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
4.4.13 Memory management fault address register (MMFSR) . . . . . . . . . . . . 240
4.4.14 Hard fault status register (HFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
4.4.15 Memory management fault address register (MMFAR) . . . . . . . . . . . . 242
4.4.16 Bus fault address register (BFAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
4.4.17 Auxiliary fault status register (AFSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 243
4.4.18 System control block design hints and tips . . . . . . . . . . . . . . . . . . . . . 243
4.4.19 SCB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.5 SysTick timer (STK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
4.5.1 SysTick control and status register (STK_CTRL) . . . . . . . . . . . . . . . . 247
4.5.2 SysTick reload value register (STK_LOAD) . . . . . . . . . . . . . . . . . . . . . 248

ST STM32H7 Series Specifications

General

Brand	ST
Model	STM32H7 Series
Category	Computer Hardware
Language	English