Sun Microelectronics
104
UltraSPARC User’s Manual
7.7.3.1 Error Handling
The system can reply with S_RTO (time-out, typically if the address is for unim-
plemented memory), or S_ERR (bus error, typically if the access is illegal). These
in turn generate data access or instruction access error exceptions as described in
Chapter 11, “Error Handling.”
7.7.4 ReadToDiscard (P_RDD_REQ)
Coherent Read with intent to discard after first use. Generated by UltraSPARC for
a block load miss.
No state change in Etag in the system. This is a nondestructive read from an own-
ing cache (in M | O state), or from main memory. SC provides the data to
UltraSPARC with the S_RBS reply. The DVP bit is undefined for this transaction.
Table 7-12 shows the number of outstanding ReadToDiscard transactions that
each UltraSPARC model supports.
7.7.4.1 Error Handling
The system can reply with S_RTO (time-out, typically if the address is for unim-
plemented memory), or S_ERR (bus error, typically if the access is illegal). These
in turn generate data access or instruction access error exceptions as described in
Chapter 11, “Error Handling.”
7.7.5 Writeback (P_WRB_REQ)
Writeback Request. Generated by UltraSPARC to write back a dirty victimized
block to memory. The Writeback is always associated with a preceding coherent
victimizing read transaction (with the DVP bit set) on the same cache line.
The Etag transitions to a new state based on the associated victimizing read
transaction; that is, to E state if no other processor has the data, to S state if an-
other processor shares the data, or to I state if the read fails.
Table 7-12 Supported Number of Outstanding ReadToDiscard Transactions
UltraSPARC-I UltraSPARC-II
Number 12
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