Sun Microelectronics
132
UltraSPARC User’s Manual
7.16.3 ReadToShare Block
Condition: Load miss on Processor 1; another processor (P2) has the data exclu-
sively.
If the load miss on Processor 1 victimizes a clean block instead an invalid block,
the sequence is the same.
7.16.4 ReadToShare Block
Condition: Load miss on Processor 1; another processor (P2) has a modified copy
of the block.
Table 7-27 ReadToShare One Processor Has it Exclusively
Processor 1 System Processor 2 Processor 3
Initial state: Etag{I}
P_RDS_REQ to System
Initial state: Etag{E} Initial state: Etag{I}
S_CPB_REQ to P2
P2 copies block to copyback
buffer
P2 updates Etag{E → S}
P_SACK reply to System
S_CRAB reply to P2
S_RBS reply to P1
P1 updates Etag{I → S} Final state: Etag{S} Final state: No change
Table 7-28 ReadToShare Dirty Block
Processor 1 System Processor 2 Processor 3
Initial state: Etag{I}
P_RDS_REQ to System
Initial state: Etag{O} Initial state: Etag{S}
S_CPB_REQ to P2
P2 copies block to copyback
buffer
P_SACK reply to System
S_CRAB reply to P2
S_RBS reply to P1
P1 updates Etag{I → S} Final state: No change Final state: No change
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