Sun Microelectronics
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7. UltraSPARC External Interfaces
When Processor 2’s initial state is Etag{M} the sequence is the same, except that
Processor 2 transitions to Etag{O}. Processor 3 initial state is Etag{I} by definition
in this case, and no transaction is generated to it by SC.
When Processor 2’s initial state is Etag{S} the sequence is the same.
When the miss victimizes a clean block instead of an invalid block, the sequence
is the same.
7.16.5 ReadToOwn Block
Condition: Store miss on Processor 1; Processors 2 and 3 each have clean copies of
the block.
When the miss victimizes a clean block instead of an invalid block the sequence
is the same.
When Processor 2’s initial state is Etag{M or O}, the sequence is the same.
7.16.6 ReadToOwn Block
Condition: Store hit on Processor 1; another processor (P2) owns the block.
Table 7-29 ReadToOwn Shared Block
Processor 1 System Processor 2 Processor 3
Initial state: Etag{I}
P_RDO_REQ to System
Initial state: Etag{S} Initial state: Etag{S}
S_CPI_REQ to P2
S_INV_REQ to P3
P2 copies block to copyback
buffer
P2 updates Etag{S → I}
P_SACK reply to System
P3 updates Etag{S → I}
P_SACK reply to System
S_CRAB reply to P2
S_RBU reply to P1
P1 updates Etag{I → M} Final state: Etag{I}
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