Sun Microelectronics
183
11. Error Handling
Refer to Table 10-1, “Machine State After Reset and in RED_state,” on page 172
for the state of this register after reset.
Name: ASI_ASYNC_FAULT_ADDRESS
ASI=4D
16
, VA<63:0>=0
16
PA: Address information for the most recently captured error.
1.
No address information captured.
2.
Writeback and copyout are also known as victimization and coherent intervention respectively.
3.
On copyout, the sender logs the error but does not trap; the requester gets an UE error. Software will cross-call other masters and
check for the origination of the error by checking the CP bit of the other AFSR registers.
4.
UltraSPARC’s UDB corrupts the ECC for data with bad parity from UltraSPARC.
5.
E_SYND = “ECC syndrome”; P_SYND = “parity syndrome:; ETS = “E-Cache Tag Parity Syndrome.”
6.
I = instruction_access_error trap; D = data_access_error trap; C= corrected_ECC_error trap; POR= Power-on Reset trap.
Table 11-5 Asynchronous Fault Address Register
Bits Field Use RW
<63:41> Reserved —R
<40:4> PA<40:4> Physical address of faulting transaction RW
<3:0> Reserved —R
Table 11-6 Error Detection and Reporting in AFAR and AFSR
Error Type PA SYNDROME
5
Trap
PRIV
Captured?
Trap Type
6
Updated
Status
SW Cache
Flush
Uncorrectable ECC Y E_SYND Deferred Y I, D UE Yes if
cacheable
Correctable ECC Y E_SYND Disrupting N C CE No
E-Cache parity: SF LD/Fetch N
1
P_SYND Deferred Y I, D EDP Yes
E-Cache parity:
2
UDB writeback N
1
P_SYND Disrupting N D WP No
E-Cache parity:
3
UDB copyout N
1
P_SYND —
3
N — CP No
UltraSPARC → UDB
4
no logging or report
UDB → SF N
1
P_SYND Deferred Y I, D LDP Yes if
cacheable
Bus Error Y — Deferred Y I, D BERR Yes if
cacheable
Time-out Y — Deferred Y I, D TO Yes if
cacheable
IV with UE N — Deferred Y D IVUE No
Tag parity N ETS fatal error N POR from
system
ETP power on
clear
Incoming SAP N — fatal error N POR from
system
ISAP power on
clear
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