Sun Microelectronics
192
UltraSPARC User’s Manual
LDDFA Load double floating-point from alternate space A.26
LDDFA Zero-extended 8-/16-bit load to a double precision FP register ✓ 13.6.2
LDF Load floating-point A.25
LDFA Load floating-point from alternate space A.26
LDFSR Load floating-point state register lower A.25
LDQF Load quad floating-point A.25
LDQFA Load quad floating-point from alternate space A.26
LDSB Load signed byte A.27
LDSBA Load signed byte from alternate space A.28
LDSH Load signed halfword A.27
LDSHA Load signed halfword from alternate space A.28
LDSTUB Load-store unsigned byte A.27
LDSTUBA Load-store unsigned byte in alternate space A.28
LDSW Load signed word A.27
LDSWA Load signed word from alternate space A.28
LDUB Load unsigned byte A.27
LDUBA Load unsigned byte from alternate space A.28
LDUH Load unsigned halfword A.27
LDUHA Load unsigned halfword from alternate space A.28
LDUW Load unsigned word A.27
LDUWA Load unsigned word from alternate space A.28
LDX Load extended A.27
LDXA Load extended from alternate space A.28
LDXFSR Load extended floating-point state register A.25
MEMBAR Memory barrier A.31
MOVcc Move integer register if condition is satisfied A.34
MOVr Move integer register on contents of integer register A.35
MULScc Multiply step (and modify condition codes) A.38
MULX Multiply 64-bit integers A.36
NOP No operation A.39
OR (ORcc) Inclusive-or (and modify condition codes) A.31
ORN (ORNcc) Inclusive-or not (and modify condition codes) A.31
PDIST Distance between 8 8-bit components ✓ 13.5.9
POPC Population count A.40
PREFETCH
1
Prefetch data A.41
PREFETCHA
1
Prefetch data from alternate space A.41
PST Eight 8-bit/4 16-bit/2 32-bit partial stores ✓ 13.6.1
RDASI Read ASI register A.43
RDASR Read ancillary state register A.43
RDCCR Read condition codes register A.43
RDFPRS Read floating-point registers state register A.43
RDPC Read program counter A.43
Table 12-1 Complete UltraSPARC Instruction Set (Continued)
Opcode Description Ext Ref
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