Sun Microelectronics
200
UltraSPARC User’s Manual
Description:
The standard versions of these instructions perform four 16-bit or two 32-bit par-
titioned adds or subtracts between the corresponding fixed point values con-
tained in the source operands (rs1, rs2). For subtraction, rs2 is subtracted from rs1.
The result is placed in the destination register (rd).
The single precision version of these instructions (FPADD16S, FPSUB16S,
FPADD32S, FPSUB32S) perform two (16-bit) or one (32-bit) partitioned adds or
subtracts.
Note: For good performance, do not use the result of a single FPADD as part of
a 64-bit graphics instruction source operand in the next instruction group.
Similarly, do not use the result of a standard FPADD as a 32-bit graphics
instruction source operand in the next instruction group.
Traps:
fp_disabled
13.5.3 Pixel Formatting Instructions
Format (3):
opcode opf operation
FPACK16
0 0011 1011
Four 16-bit packs
FPACK32
0 0011 1010
Two 32-bit packs
FPACKFIX
0 0011 1101
Four 16-bit packs
FEXPAND
0 0100 1101
Four 16-bit expands
FPMERGE
0 0100 1011
Two 32-bit merges
Suggested Assembly Language Syntax
fpack16
freg
rs2
,
freg
rd
fpack32
freg
rs1
,
freg
rs2
,
freg
rd
fpackfix
freg
rs2
,
freg
rd
fexpand
freg
rs2
,
freg
rd
fpmerge
freg
rs1
,
freg
rs2
,
freg
rd
10 11 0110 rs2rd rs1
31 141924 18 13 02530 29 4
opf
5
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