Sun Microelectronics
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UltraSPARC User’s Manual
enabled, an
fp_exception_other
(with FSR.ftt=2,
unfinished_FPop
) trap is generated.
System software will properly handle these cases and resume execution. If the ex-
ception is not enabled, the actual result status is used to update the aexec bits of
the fsr.
Note: Major performance degradation may be observed while running with the
inexact exception enabled.
14.3.3 Quad-Precision Floating-Point Operations (Impdep #3)
All quad-precision floating-point instructions, listed in Table 14-6, cause an
fp_exception_other
(with FSR.ftt=3,
unimplemented_FPop
) trap. These operations are
emulated in system software.
14.3.4 Floating Point Upper and Lower Dirty Bits in FPRS Register
The FPRS_dirty_upper (DU) and FPRS_dirty_lower (DL) bits in the Floating-
Point Registers State (FPRS) Register are set when an instruction that modifies the
corresponding upper and lower half of the floating-point register file is dis-
patched. Floating-point register file modifying instructions include floating-point
operate, graphics, floating-point loads and block load instructions.
Table 14-6 Unimplemented Quad-Precision Floating-Point Instructions
Instruction Description
F{s,d}TOq Convert single-/double- to quad-precision floating-point
F{i,x}TOq Convert 32-/64-bit integer to quad-precision floating-point
FqTO{s,d} Convert quad- to single-/double-precision floating-point
FqTO{i,x} Convert quad-precision floating-point to 32-/64-bit integer
FCMP{E}q Quad-precision floating-point compares
FMOVq Quad-precision floating-point move
FMOVqcc Quad-precision floating-point move, if condition is satisfied
FMOVqr Quad-precision floating-point move if register match condition
FABSq Quad-precision floating-point absolute value
FADDq Quad-precision floating-point addition
FDIVq Quad-precision floating-point division
FdMULq Double- to quad-precision floating-point multiply
FMULq Quad-precision floating-point multiply
FNEGq Quad-precision floating-point negation
FSQRTq Quad-precision floating-point square root
FSUBq Quad-precision floating-point subtraction
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