Sun Microelectronics
257
15. SPARC-V9 Memory Models
• A MEMBAR #StoreLoad must be used to prevent a load from bypassing a
prior store, if Strong Sequential Order is desired.
• Stores are processed in program order.
• Stores cannot bypass earlier loads.
• Accesses with the E-bit set (that is, those having side-effects) are all strongly
ordered with respect to each other.
• An E-Cache update is delayed on a store hit until all outstanding stores reach
global visibility. For example, a cacheable store following a noncacheable store
is not globally visible until the noncacheable store has reached global
visibility; there is an implicit MEMBAR #MemIssue between them.
15.2.2 PSO
UltraSPARC implements the following programmer-visible properties in Partial
Store Order (PSO) mode:
• Loads are processed in program order; that is, there is an implicit MEMBAR
#LoadLoad between them.
• Loads may bypass earlier stores. Any such load that bypasses such earlier
stores must check (snoop) the store buffer for the most recent store to that
address. For SPARC-V9 compatibility, a MEMBAR #Lookaside should be
used between a store and a subsequent load to the same non-cacheable
address.
• Stores cannot bypass earlier loads.
• Stores are not ordered with respect to each other. A MEMBAR must be used
for stores if stronger ordering is desired. A MEMBAR #MemIssue is needed
for ordering of cacheable after non-cacheable stores.
• Non-cacheable accesses with the E-bit set (that is, those having side-effects)
are all strongly ordered with respect to each other, but not with non-E-bit
accesses.
Note: The behavior of partial stores to noncacheable addresses (pages with the
TTE.CP=0) is dependent on the system and I/O device implementation.
UltraSPARC generates a P_NCWR_REQ operation with a byte mask
corresponding to the rs2 mask of the partial store instruction. If the system
interconnect or I/O device is unable to perform the write operation of the bytes
specified by the byte mask, an error is not signaled back to the processor.
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