Sun Microelectronics
14
UltraSPARC User’s Manual
2.2.4 Stage 4: Execution (E) Stage
Data from the integer register file is processed by the two integer ALUs during
this cycle (if the instruction group includes ALU operations). Results are comput-
ed and are available for other instructions (through bypasses) in the very next cy-
cle. The virtual address of a memory operation is also calculated during the E
Stage, in parallel with ALU computation.
FLOATING-POINT AND GRAPHICS UNIT: The Register (R) Stage of the FGU. The
floating-point register file is accessed during this cycle. The instructions are also
further decoded and the FGU control unit selects the proper bypasses for the cur-
rent instructions.
2.2.5 Stage 5: Cache Access (C) Stage
The virtual address of memory operations calculated in the E Stage is sent to the
tag RAM to determine if the access (load or store type) is a hit or a miss in the
D-Cache. In parallel the virtual address is sent to the data MMU to be translated
into a physical address. On a load when there are no other outstanding loads, the
data array is accessed so that the data can be forwarded to dependent instruc-
tions in the pipeline as soon as possible.
ALU operations executed in the E Stage generate condition codes in the C Stage.
The condition codes are sent to the PDU, which checks whether a conditional
branch in the group was correctly predicted. If the branch was mispredicted, ear-
lier instructions in the pipe are flushed and the correct instructions are fetched.
The results of ALU operations are not modified after the E Stage; the data merely
propagates down the pipeline (through the annex register file), where it is avail-
able for bypassing for subsequent operations.
FLOATING-POINT AND GRAPHICS UNIT: The X
1
Stage of the FGU. Floating-point and
graphics instructions start their execution during this stage. Instructions of laten-
cy one also finish their execution phase during the X
1
Stage.
2.2.6 Stage 6: N
1
Stage
A data cache miss/hit or a TLB miss/hit is determined during the N
1
Stage. If a
load misses the D-Cache, it enters the Load Buffer. The access will arbitrate for
the E-Cache if there are no older unissued loads. If a TLB miss is detected, a trap
will be taken and the address translation is obtained through a software routine.
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