Sun Microsystems UltraSPARC-I - Page 357

Sun Microelectronics
342
UltraSPARC User’s Manual
1.
ECAD<19:0> for UltraSPARC-II
2.
ECAT<17:0> for UltraSPARC-II
3.
LOOP_CAP present in UltraSPARC-I only
System Interface Controls
System Reply S_REPLY<3:0> 4 I
Processor Reply P_REPLY<4:0> 5 O
Address Bus Arbitration NODE_RQ<2:0> 3 I
Address Bus Request NODEX_RQ 1 O
Address Packet Valid ADR_VLD 1 I/O
SC Request for interconnect addr bus SC_RQ 1 I
SC Data Stall DATA_STALL 1 I
UDB Interface
Uncorrectable Error (High) UDB_UEH 1 I
Uncorrectable Error (Low) UDB_UEL 1 I
Correctable Error (High) UDB_CEH 1 I
Correctable Error (Low) UDB_CEL 1 I
UDB Control UDB_CNTL<4:0> 5 O
Clock Interface
Differential Clock Input A CLKA 1 I
Differential Clock Input B CLKB 1 I
PLL loop filter connection LOOP_CAP
3
1I
Low Frequency/D.C. signal DC_SPARE 1 I
UDB Clock A (copy) SDBCLKA 1 I
UDB Clock B (copy) SDBCLKB 1 I
Phase Lock Loop Bypass PLLBYPASS 1 I
Level 5 Clock L5CLK 1 O
IEEE 1149.1 (JTAG) Interface/Debug
IEEE 1149.1 Test Data Out TDO 1 O
IEEE 1149.1 Test Data Input TDI 1 I
IEEE 1149.1 Test Clock Input TCK 1 I
IEEE 1149.1 Test Mode Select TMS 1 I
IEEE 1149.1 Test Reset Input TRST_L 1 I
SRAMs Test Mode RAM_TEST 1 I
Test/Debug/Instrument Bus MISC_BIDIR<14:0> 15 I/O
Clock Stopper (debug) EXT_EVENT 1 I/O
Initialization
Reset RESET_L 1 I
XIR Reset (NMI) XIR_L 1 I
Power Down Mode EPD 1 I
Table E-8 UltraSPARC Signals (Continued)
Function Name Count I/O
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