Sun Microelectronics
360
UltraSPARC User’s Manual
privileged:
An adjective that describes (1) the state of the processor when
PSTATE.PRIV=1, that is, privileged mode; (2) processor state that is only
accessible to software while the processor is in privileged mode; e.g., privi-
leged registers, privileged ASRs, or, in general, privileged state; (3) an instruc-
tion that can be executed only when the processor is in privileged mode.
privileged mode:
The processor is operating in privileged mode when PSTATE.PRIV=1.
program counter (PC):
A register that contains the address of the instruction currently being exe-
cuted by the IU.
RED_state:
Reset, Error, and Debug state. The processor is operating in RED_state when
PSTATE.RED=1.
restricted:
An adjective used to describe an address space identifier (ASI) that may be
accessed only while the processor is operating in privileged mode.
reserved:
Used to describe an instruction field, certain bit combinations within an
instruction field, or a register field that is reserved for definition by future
versions of the architecture. A reserved field should only be written to zero
by software. A reserved register field should read as zero in hardware; soft-
ware intended to run on future versions of SPARC-V9 should not assume that
the field will read as zero or any other particular value. Throughout this doc-
ument, figures illustrating registers and instruction encodings always indi-
cate reserved fields with an em dash ‘—’.
reset trap:
A vectored transfer of control to privileged software through a fixed-address
reset trap table. Reset traps cause entry into RED_state.
rs1, rs2, rd:
The integer register operands of an instruction. rs1 and rs2 are the source reg-
isters; rd is the destination register.
shall:
A key word indicating a mandatory requirement. Designers shall implement
all such mandatory requirements to ensure inter-operability with other
SPARC-V9-conformant products. The key word “must” is used interchange-
ably with the key word shall.
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