Sun Microelectronics
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UltraSPARC User’s Manual
5.3.1 Coherence Domains
Two types of memory operations are supported in UltraSPARC: cacheable and
noncacheable accesses, as indicated by the page translation. Cacheable accesses
are inside the coherence domain; noncacheable accesses are outside the coherence
domain.
SPARC-V9 does not specify memory ordering between cacheable and noncache-
able accesses. In TSO mode, UltraSPARC maintains TSO ordering, regardless of
the cacheability of the accesses. For SPARC-V9 compatibility while in PSO or
RMO mode, a MEMBAR #Lookaside should be used between a store and a sub-
sequent load to the same noncacheable address. See Section 8, “Memory Models,”
in The SPARC Architecture Manual, Version 9 for more information about the
SPARC-V9 memory models.
Note: On UltraSPARC, a MEMBAR #Lookaside executes more efficiently than
a MEMBAR #StoreLoad.
5.3.1.1 Cacheable Accesses
Accesses that fall within the coherence domain are called cacheable accesses.
They are implemented in UltraSPARC with the following properties:
• Data resides in real memory locations.
• They observe supported cache coherence protocol(s).
• The unit of coherence is 64 bytes.
5.3.1.2 Non-Cacheable and Side-Effect Accesses
Accesses that are outside the coherence domain are called noncacheable accesses.
Some of these memory (-mapped) locations may have side-effects when accessed.
They are implemented in UltraSPARC with the following properties:
• Data may or may not reside in real memory locations.
• Accesses may result in program-visible side-effects; for example, memory-
mapped I/O control registers in a UART may change state when read.
• They may not observe supported cache coherence protocol(s).
• The smallest unit in each transaction is a single byte.
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