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5. Cache and Memory Interactions
Noncacheable accesses with the E-bit set (that is, those having side-effects) are all
strongly ordered with respect to other noncacheable accesses with the E-bit set. In
addition, store buffer compression is disabled for these accesses. Speculative
loads with the E-bit set cause a
data_access_exception
trap (with SFSR.FT=2, spec-
ulative load to page marked with E-bit).
Note: The side-effect attribute does not imply noncacheability.
5.3.1.3 Global Visibility and Memory Ordering
A memory access is considered globally visible when it has been acknowledged
by the system. In order to ensure the correct ordering between the cacheable and
noncacheable domains, explicit memory synchronization is needed in the form of
MEMBARs or atomic instructions. Code Example 5-1 illustrates the issues in-
volved in mixing cacheable and noncacheable accesses.
Code Example 5-1 Memory Ordering and MEMBAR Examples
Assume that all accesses go to non-side-effect memory locations.
Process A:
While (1)
{
Store D1:data produced
1 MEMBAR #StoreStore (needed in PSO, RMO)
Store F1:set flag
While F1 is set (spin on flag)
Load F1
2 MEMBAR #LoadLoad | #LoadStore (needed in RMO)
Load D2
}
Process B:
While (1)
{
While F1 is cleared (spin on flag)
Load F1
2 MEMBAR #LoadLoad | #LoadStore (needed in RMO)
Load D1
Store D2
1 MEMBAR #StoreStore (needed in PSO, RMO)
Store F1:clear flag
}
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