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5. Cache and Memory Interactions
5.3.2.4 MEMBAR #StoreStore and STBAR
Forces all stores after the MEMBAR to wait until all stores before the MEMBAR
have reached global visibility.
Note: STBAR has the same semantics as MEMBAR #StoreStore; it is included
for SPARC-V8 compatibility.
Note: The above four MEMBARs do not guarantee ordering between cacheable
accesses after noncacheable accesses.
5.3.2.5 MEMBAR #Lookaside
SPARC-V9 provides this variation for implementations having virtually tagged
store buffers that do not contain information for snooping.
Note: For SPARC-V9 compatibility, this variation should be used before issuing
a load to an address space that cannot be snooped.
5.3.2.6 MEMBAR #MemIssue
Forces all outstanding memory accesses to be completed before any memory ac-
cess instruction after the MEMBAR is issued. It must be used to guarantee order-
ing of cacheable accesses following non-cacheable accesses. For example, I/O
accesses must be followed by a MEMBAR #MemIssue before subsequent cache-
able stores; this ensures that the I/O accesses reach global visibility before the
cacheable stores after the MEMBAR.
Note: MEMBAR #MemIssue is different from the combination of MEMBAR
#LoadLoad | #LoadStore | #StoreLoad | #StoreStore. MEMBAR
#MemIssue orders cacheable and noncacheable domains; it prevents memory
accesses after it from issuing until it completes.
5.3.2.7 MEMBAR #Sync (Issue Barrier)
Forces all outstanding instructions and all deferred errors to be completed before
any instructions after the MEMBAR are issued.
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