Sun Microelectronics
34
UltraSPARC User’s Manual
Note: MEMBAR #Sync is a costly instruction; unnecessary usage may result in
substantial performance degradation.
5.3.2.8 Self-Modifying Code (FLUSH)
The SPARC-V9 instruction set architecture does not guarantee consistency be-
tween code and data spaces. A problem arises when code space is dynamically
modified by a program writing to memory locations containing instructions. LISP
programs and dynamic linking require this behavior. SPARC-V9 provides the
FLUSH instruction to synchronize instruction and data memory after code space
has been modified.
In UltraSPARC, a FLUSH behaves like a store instruction for the purpose of
memory ordering. In addition, all instruction (pre-)fetch buffers are invalidated.
The issue of the FLUSH instruction is delayed until previous (cacheable) stores
are completed. Instruction (pre-)fetch resumes at the instruction immediately af-
ter the FLUSH.
5.3.3 Atomic Operations
SPARC-V9 provides three atomic instructions to support mutual exclusion. These
instructions behave like both a load and a store, but the operations are carried out
indivisibly. Atomic instructions may be used only in the cacheable domain.
An atomic access with a restricted ASI in unprivileged mode (PSTATE.PRIV=0)
causes a
privileged_action
trap. An atomic access with a noncacheable address caus-
es a
data_access_exception
trap (with SFSR.FT=4, atomic to page marked non-
cacheable). An atomic access with an unsupported ASI causes a
data_access_exception
trap (with SFSR.FT=8, illegal ASI value or virtual address).
Table 5-1 lists the ASIs that support atomic accesses.
Table 5-1 ASIs that Support SWAP, LDSTUB, and CAS
ASI Name Access
ASI_NUCLEUS{_LITTLE} Restricted
ASI_AS_IF_USER_PRIMARY{_LITTLE} Restricted
ASI_AS_IF_USER_SECONDARY{_LITTLE} Restricted
ASI_PRIMARY{_LITTLE} Unrestricted
ASI_SECONDARY{_LITTLE} Unrestricted
ASI_PHYS_USE_EC{_LITTLE} Unrestricted
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