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5. Cache and Memory Interactions
Note: Atomic accesses with non-faulting ASIs are not allowed, because these
ASIs have the load-only attribute.
5.3.3.1 SWAP Instruction
SWAP atomically exchanges the lower 32 bits in an integer register with a word
in memory. This instruction is issued only after store buffers are empty. Subse-
quent loads interlock on earlier SWAPs. A cache miss will allocate the corre-
sponding line.
Note: If a page is marked as virtually-non-cacheable but physically cacheable,
allocation is done to the E-Cache only.
5.3.3.2 LDSTUB Instruction
LDSTUB behaves like SWAP, except that it loads a byte from memory into an in-
teger register and atomically writes all ones (FF
16
) into the addressed byte.
5.3.3.3 Compare and Swap (CASX) Instruction
Compare-and-swap combines a load, compare, and store into a single atomic in-
struction. It compares the value in an integer register to a value in memory; if
they are equal, the value in memory is swapped with the contents of a second in-
teger register. All of these operations are carried out atomically; in other words,
no other memory operation may be applied to the addressed memory location
until the entire compare-and-swap sequence is completed.
5.3.4 Non-Faulting Load
A non-faulting load behaves like a normal load, except that:
• It does not allow side-effect access. An access with the E-bit set causes a
data_access_exception
trap (with SFSR.FT=2, Speculative Load to page marked
E-bit).
• It can be applied to a page with the NFO-bit set; other types of accesses will
cause a
data_access_exception
trap (with SFSR.FT=10
16
, Normal access to page
marked NFO).
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