Sun Microelectronics
58
UltraSPARC User’s Manual
Compatibility Note
The single context register of the SPARC-V8 Reference MMU has been replaced in
UltraSPARC by the three context registers shown in Figures 6-4, 6-5, and 6-6.
Note: A STXA to the context registers requires either a MEMBAR #Sync,
FLUSH, DONE, or RETRY before the point that the effect must be visible to data
accesses. Either a FLUSH, DONE, or RETRY is needed before the point that the
effect must be visible to instruction accesses: MEMBAR #Sync is not sufficient. In
either case, one of these instructions must be executed before the next translating
or bypass store or load of any type. This is necessary to avoid corrupting data.
6.9.4 I-/D-MMU Synchronous Fault Status Registers (SFSR)
The I- and D-MMU each maintain their own SFSR register, which is defined as
follows:
Figure 6-7 I- and D-MMU Synchronous Fault Status Register Format
ASI: The ASI field records the 8-bit ASI associated with the faulting
instruction. This field is valid for both D-MMU and I-MMU SFSRs and
for all traps in which the FV bit is set. JMPL and RETURN
mem_address_not_aligned
traps set the default ASI, as does a trapping non-
alternate load or store; that is, to ASI_PRIMARY for PSTATE.CLE=0, or
ASI_PRIMARY_LITTLE otherwise.
FT: The Fault Type field indicates the exact condition that caused the
recorded fault, according to Table 6-11. In the D-MMU the Fault Type
field is valid only for
data_access_exception
traps; there is no ambiguity in
all other MMU trap cases. Note that the hardware does not priority-
encode the bits set in the fault type register; that is, multiple bits may be
set. The FT field in the D-MMU SFSR reads zero for traps other than
data_access_exception
. The FT field in the I-MMU SFSR always reads zero
for
instruction_access_MMU_miss
, and either 01
16
, 20
16
, or 40
16
for
instruction_access_exception
, as all other fault types do not apply.
63 2324 15 1316 14 7 5 3 1642 0
— ASI
—
FT E W
OF
VW
C
T
P
R
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