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6. MMU Internal Architecture
6.9.2 I-/D-TSB Tag Target Registers
The I- and D-TSB Tag Target registers are simply bit-shifted versions of the data
stored in the I- and D-Tag Access registers, respectively. Since the I- or D-Tag Ac-
cess register is updated on an I- or D-TLB miss, respectively, the I- and D-Tag Tar-
get registers appear to software to be updated on an I or D TLB miss.
Figure 6-3 MMU Tag Target Registers (Two Registers)
I/D Context<12:0>: The context associated with the missing virtual address.
I/D VA<63:22>: The most significant bits of the missing virtual address.
6.9.3 Context Registers
The context registers are shared by the I- and D-MMUs. The Primary Context
Register is defined as follows:
Figure 6-4 D-MMU Primary Context Register
PContext: Context identifier for the primary address space.
The Secondary Context register is defined as follows:
Figure 6-5 D-MMU Secondary Context Register
SContext: Context identifier for the secondary address space.
The Nucleus Context register is hardwired to zero:
Figure 6-6 D-MMU Nucleus Context Register
63 61 47 4160 48 42 0
Context000 — VA<63:22>
63
13 12 0
— PContext
63 13 12 0
— SContext
63 0
0000000000000000000000000000000000000000000000000000000000000000
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