Sun Microelectronics
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7. UltraSPARC External Interfaces
The E-Cache consists of two parts:
• The E-Cache Tag RAMs, which contain the physical tags of the cached lines,
along with a small amount of state information, and
• The E-Cache Data RAMs, which contain the actual data for each cache line.
The E-Cache RAMs are commodity parts (synchronous static RAMs) that operate
synchronously with UltraSPARC. Each byte within the E-Cache RAMs is protect-
ed by a parity bit; there are three parity bits for the tags and 16 parity bits for da-
ta. Table 7-3 lists the E-Cache sizes that each UltraSPARC model supports.
Note: Software can determine the E-Cache size at boot time by probing with
diagnostic writes to addresses 2
k
, 2
k+1
, 2
k+2
. . . until wrap-around occurs.
The E-Cache’s clients are:
• Load buffer: All loads that miss the D-Cache are sent on to the E-Cache.
• Store buffer: All cacheable stores go to the E-Cache (because the D-Cache is
write-through); the order of stores with respect to loads is determined by the
memory ordering model.
• Prefetch unit: All I-Cache misses generate a request to the E-Cache.
• UDB: The UDB returns data from main memory during E-Cache misses or
loads to noncacheable locations. Writebacks (the process of writing a dirty line
back to memory before it is refilled), generate data transfers from the E-Cache
to the UDB, controlled entirely by the CPU. Copyback requests from the
system also generate transfers from the E-Cache to the UDB.
E-Cache client transactions have the following relative priorities:
• The request for the second 16 bytes of data from the I-Cache/Prefetch Unit.
• External Cache Unit (ECU) requests.
• Load buffer requests.
Table 7-3 Supported E-Cache Sizes (Same as Table 1-5)
E-Cache Size UltraSPARC-I UltraSPARC-II
512 Kb ✓✓
1 Mb ✓✓
2 Mb ✓✓
4 Mb ✓✓
8 Mb ✓
16 Mb ✓
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