Tektronix Keithley 4225-PMU User Manual

Model 4200A
-SCS Pulse Card (PGU and PMU) User's Manual Section 2:
Connections
4200A-PMU-900-01 Rev. B March 2023 2-27
Coping with the load-line effect
There are several ways of working with this effect. The simplest one is to program the DUT load into
the pulse card channel using the pulse_load function, or setting the Pulse Load value in the KPulse
(on page 5-1) virtual front panel. The pulse card calculates the appropriate V
INT
to output so that the
V
DUT
pulse waveform, specified by pulse_vlow and pulse_vhigh, has the correct levels. This
works well for high impedance devices or device terminals (R
DUT
= 1 kΩ), such as the gate terminal
on a CMOS field effect transistor (FET). Unfortunately, many times R
DUT
is not known or varies. A key
example of a varying R
DUT
is the drain-source resistance during a V
D
-I
D
sweep, where R
DS
is changing
from point-to-point and sweep-to-sweep.
There is basically only one way to handle this situation, with two different levels of implementation. In
general, assume the DUT is a FET. If the test consists of a single or limited number of gate and drain
test points, the necessary voltages can be determined by pre-characterizing each unique set of
test conditions.
This pre-characterization requires some way to measure the pulse heights, which is typically done
using an oscilloscope and an iterative trial and error approach. Each test voltage needs to be
measured, with the pulse levels adjusted until the correct voltage is reached. Record each pulse level
required to reach the required V
DUT
levels.
For information on the LPT commands listed above, refer to Model 4200A-SCS LPT
Library Programming.
The 4225-PMU has built-in load-line effect compensation. For details, see Load-line effect
compensation (LLEC) for the PMU (on page 2-24).
LLEC maintains even voltage spacing
Another advantage of using LLEC is that it maintains even voltage spacing during the test. For
example, if the pulse sweep uses 250 mV steps, DUT voltage and current measurements will be
performed at every 250 mV step. Data that is generated using even voltage spacing is ready to be fed
into a mathematical model.
When not using LLEC, uneven voltage spacing may result due to load-line effect. The following figure
shows load-line effect on a FET family of curves. The blue curves were generated with LLEC enabled
and the green curves were generated with LLEC disabled. The Vg was increased for the green
curves to provide separation between the curves.
In the following figure, each blue curve (LLEC on) is the result of a sweep from 0 to 6 V using 250 mV
steps. Notice that the 24 pulse-measure points are evenly spaced.

Tektronix Keithley 4225-PMU Specifications

General

Brand	Tektronix
Model	Keithley 4225-PMU
Category	Computer Hardware
Language	English