Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 144
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Dbg_Intr
3
Core O
Debug interrupt output, set when a Performance Monitor counter
overflows, available when
C_DEBUG_ENABLED is set to 2
(Extended).
MB_Error
3
Core O
Pipeline is halted due to a missed exception, when
C_FAULT_TOLERANT is set to 1.
Sleep
3
Core O
MicroBlaze is in sleep mode after executing a SLEEP instruction
or by setting Reset_Mode[0:1] to 10, all external accesses are
completed, and the pipeline is halted.
Hibernate
3
Core O
MicroBlaze is in sleep mode after executing a HIBERNATE
instruction, all external accesses are completed, and the pipeline
is halted.
Suspend
3
Core O
MicroBlaze is in sleep mode after executing a SUSPEND
instruction, all external accesses are completed, and the pipeline
is halted.
Wakeup[0:1]
3
Core I
Wake MicroBlaze from sleep mode when either or both bits are
set to 1. Ignored if MicroBlaze is not in sleep mode. The signals
are individually synchronized to Clk according to the parameter
C_ASYNC_WAKEUP[0:1].
Dbg_Wakeup
3
Core O
Debug request that external logic should wake MicroBlaze from
sleep mode with the
Wakeup signal, to allow debug access.
Synchronous to Dbg_Update.
Pause
3
Core I
When this signal is set MicroBlaze pipeline will be paused after
completing all ongoing bus accesses, and the
Pause_Ack signal
will be set. When this signal is cleared again MicroBlaze will
continue normal execution where it was paused.
Pause_Ack
3
Core O
MicroBlaze is in pause mode after the Pause input signal has
been set.
Dbg_Continue
3
Core O
Debug request that external logic should clear the Pause signal,
to allow debug access.
Non_Secure[0:3]
3
Core I
Determines whether AXI accesses are non-secure or secure. The
default value is binary 0000, setting all interfaces to be secure.
Bit 0 = M_AXI_DP
Bit 1 = M_AXI_IP
Bit 2 = M_AXI_DC
Bit 3 = M_AXI_IC
Lockstep_...
Core IO
Lockstep signals for high integrity applications. See Table 3-13
for details.
Dbg_...
Core IO
Debug signals from MDM. See Table 3-15 for details.
Trace_...
Core O
Trace signals for real time HW analysis. See Table 3-16 for details.
1. Only used with C_USE_INTERRUPT = 2, for low-latency interrupt support.
2. MicroBlaze is a synchronous design clocked with the Clk signal, except for serial hardware debug logic, which is clocked with
the
Dbg_Clk signal. If serial hardware debug logic is not used, there is no minimum frequency limit for Clk. However, if
serial hardware debug logic is used, there are signals transferred between the two clock regions. In this case
Clk must have
a higher frequency than
Dbg_Clk.
3. Only visible when
C_ENABLE_DISCRETE_PORTS = 1.
Table 3-1: Summary of MicroBlaze Core I/O (Cont’d)
Signal Interface I/O Description
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module