Xilinx MicroBlaze - Page 159

MicroBlaze Processor Reference Guide 160
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Back-to-Back Write Operation
Back-to-Back Read Operation
X-Ref Target - Figure 3-8
Figure 3-8: LMB Back-to-Back Write Operation
A0
BE0
D0
A1
BE1
D1
A2
BE2
D2
A3
BE3
D3
A4
BE4
D4
Don’t Care
Don’t Care
Don’t Care
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Wirte_Strobe
Data_Read
Ready
Wait
CE
UE
X19792-091217
X-Ref Target - Figure 3-9
Figure 3-9: LMB Back-to-Back Read Operation
A0 A1 A2 A3 A4
D0 D1 D2 D3 D4
Don’t Care
Don’t Care
Don’t Care
Clk
Addr
Byte_Enable
Data_Write
AS
Read_Strobe
Wirte_Strobe
Data_Read
Ready
Wait
CE
UE
X19793-091217
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