Xilinx MicroBlaze - Page 161

MicroBlaze Processor Reference Guide 162
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Read and Write Data Steering
The MicroBlaze data-side bus interface performs the read steering and write steering
required to support the following transfers:
• byte, halfword, and word transfers to word devices
• byte and halfword transfers to halfword devices
• byte transfers to byte devices
MicroBlaze does not support transfers that are larger than the addressed device. These
types of transfers require dynamic bus sizing and conversion cycles that are not supported
by the MicroBlaze bus interface. Data steering for read cycles are shown in
Table 3-9 and
Table 3-10, and data steering for write cycles are shown in Table 3-11 and Table 3-12.
Big endian format is only available when using the MMU in virtual or protected mode
(
C_USE_MMU > 1) or when reorder instructions are enabled (C_USE_REORDER_INSTR = 1).
Table 3-9: Big Endian Read Data Steering (Load to Register rD)
Address
[LSB-1:LSB]
Byte_Enable
[0:3]
Transfer Size
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
11 0001 byte Byte3
10 0010 byte Byte2
01 0100 byte Byte1
00 1000 byte Byte0
10 0011 halfword Byte2 Byte3
00 1100 halfword Byte0 Byte1
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 3-10: Little Endian Read Data Steering (Load to Register rD)
Address
[LSB-1:LSB]
Byte_Enable
[0:3]
Transfer Size
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
11 1000 byte Byte0
10 0100 byte Byte1
01 0010 byte Byte2
00 0001 byte Byte3
10 1100 halfword Byte0 Byte1
00 0011 halfword Byte2 Byte3
00 1111 word Byte0 Byte1 Byte2 Byte3
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