REMOTE OPERATION STATUS COMMANDS
4-199
Status byte register. This 8−bit register (pages 4-203 and 4-204) is used to represent particular
conditions or events in an instrument. The status byte register (defined by IEEE 488.1) is read by
using the *STB? command or by serial poll. When read by serial poll, an SRQ (service request) is
generated that alerts the controller. Associated with the status byte register is the service request
enable register, which allows control over which bits of the status byte contribute towards the
generation of the SRQ signal. When read by *STB?, bit 6 of the status byte is known as the
master summary status function (MSS), and is the OR function of the other seven bits of the
register.
Standard event register. This 8−bit register (page 4-207) extends the status reporting structure to
cover various other events, defined by IEEE 488.2. The register is read by *ESR? The standard
event enable register allows control over which bits of the standard event register affect the
summary bit output (ESB). The summary bit is recorded in bit 5 of the status byte.
Operation status register. This 16−bit register (page 4-209), defined in SCPI, further extends the
status reporting structure by providing information about what the instrument is doing. It is read
by the STATus:OPERation:CONDition? or STATus:OPERation[:EVENt]? command. The
summary bit output of the register is recorded in bit 7 of the status byte.
Questionable status register. This 16−bit register (page 4-208), defined in SCPI, gives
information about factors affecting the quality of signal generation. It is read by the
STATus:QUEStionable:CONDition? or STATus:QUEStionable[:EVENt]? command. The
summary bit output of the register is recorded in bit 3 of the status byte.
Questionable power status register. This 16−bit register (page 4-209) further extends the
questionable status register by providing power condition information. It is read by the
STATus:QUEStionable:POWer:CONDition? or STATus:QUEStionable:POWer[:EVENt]?
command and recorded in bit 3 of the questionable status register.
Questionable frequency status register. This 16−bit register (page 4-210) further extends the
questionable status register by providing frequency condition information. It is read by the
STATus:QUEStionable:FREQuency:CONDition? or
STATus:QUEStionable:FREQuency[:EVENt]? command and recorded in bit 5 of the questionable
status register.
Questionable modulation status register. This 16−bit register (pages 4-210 to 4-213) further
extends the questionable status register by providing modulation condition information from the
AM, FM, PM, PULM, IQ and ARB and DM questionable modulation registers. It is read by the
STATus:QUEStionable:MODulation:CONDition? or
STATus:QUEStionable:MODulation[:EVENt]? command and recorded in bit 7 of the
questionable status register.
Questionable calibration status register. This 16−bit register (page 4-214) further extends the
questionable status register by providing calibration condition information. It is read by the
STATus:QUEStionable:CALibration:CONDition? or
STATus:QUEStionable:CALibration[:EVENt]? command and recorded in bit 8 of the
questionable status register.
Questionable ROSCillator status register. This 16−bit register (page 4-214) further extends the
questionable status register by providing reference oscillator condition information. It is read by
the STATus:QUEStionable:ROSCillator:CONDition? or
STATus:QUEStionable:ROSCillator[:EVENt]? command and recorded in bit 9 of the questionable
status register.
The output queue (page 4-205) temporarily stores responses to query commands received by the
instrument until they can be read by the controller. The error queue (page 4-205) temporarily
stores up to 20 error messages. Each time the instrument detects an error, it places a message in
the queue; each item contains an error number, defined in SCPI, and an error message. When the
SYSTem:ERRor? query is sent, the message at the head of the error queue is moved to the output
queue so it can be read by the controller.
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