Local ClockLocal Clock
Parent ClockParent Clock
Foreign MasterForeign Master
66..11..33..66 IEEE 1588v2IEEE 1588v2
Touching the IEEE 1588v2IEEE 1588v2 button in the status area of the Ports SetupPorts Setup screen
displays the status shown below.
This screen presents information about the status of the IEEE 1588 clock.
StateState
Shows the current clock state of the ports (MASTERMASTER/SLAVESLAVE). INIT.INIT. appears
when a unicast slave is stuck in INIT-state until the master clock grants access.
OffsetOffset
Shows the current offset from the master clock.
Mean path delayMean path delay
Shows the mean path delay, which is the time from master to slave back to
master again, divided by two.
Delay asymmetryDelay asymmetry
Shows the value calculated from the received INTERFACE RATE TLV only
when profile is set to G.8275.2G.8275.2.
For details, refer to the standards listed on the Profile option tab.
Sync timeoutSync timeout
Shows the current status of Sync Message reception. The Lamp icon becomes
red if no Sync Message has been received within five times the Sync interval.
IdentityIdentity
Shows the identity of a slave's parent clock.
Port numberPort number
Shows the port number of a slave's parent clock.
Provides a list of detected foreign masters. The identity of the current master is
shown in the field, the other masters are listed in a drop-down menu.
Port numberPort number
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