Configuring the Camera
BASLER L304
kc 4-9
Draft
Camera Status Inquiry
The camera has been programmed to detect several error conditions. When an error condition is detected,
a flag is set. The camera status inquiry register lets you read the error flags.
Register Base Address: 0x0C00
Field Name: Register Status Offset: 0x0000 Size: 1 Byte Type: Read only
Description: The integer value in this field indicates the status of this inquiry register:
0x00 = The register is not available
0x01 = The register is available.
Field Name: Camera Status Offset: 0x0001 Size: 4 Bytes Type: Read only
Description: Each bit in this field specifies an error condition (see table below). Bit 0 is the least signifi-
cant bit. If a bit is set to 1, the error condition assigned to that bit is present. If the bit is set
to 0, the error is not present.
Bit Description
0 Reserved
1 The camera is booting or is busy performing an internal operation (such as
generating shading values).
2 A reset has occurred. This bit is auto-cleared on read.
3 Parameter error, for example, a parameter has been set to a value that is out
of range or not allowed.
4 A user set load has failed.
5 A file operation has failed.
6 An over-voltage situation has been detected. This bit clears when the cam-
era is reset or is powered off and back on.
7 A binary read/write command protocol error has been detected. For more in-
formation about the error, read the Binary Command Status Inquiry register
(see page 4-11). This bit is auto-cleared on read.
8 ... 15 Reserved
16 An FPGA not ready error has occurred. For more information about the error,
read the FPGA Status Inquiry register (see page 4-10). This bit clears when
you read the FPGA Status Inquiry register.
17 A trigger error has occurred. Either the line rate has been exceeded or the
ExSync signal is missing. For more information about the error, read the
FPGA Status Inquiry register (see page 4-10). This bit clears when you read
the FPGA Status Inquiry register.
18 Illumination warning. High clipping, low clipping or a dark pixel error has oc-
curred. For more information about the error, read the FPGA Status Inquiry
register (see page 4-10). This bit clears when you read the FPGA Status In-
quiry register.
19 The last shading value generation process failed.
The DSNU shading value generation process can fail if the pixel values in
the lines captured during the generation process are too high. (The process
should be performed in darkness or in very low light conditions.)
The PRNU shading value generation process can fail if the values for the
darkest pixels in the captured lines are less than 1/2 of the values for the
lightest pixels. This problem is often caused by extremely non-uniform light-
ing or by poor quality optics.
This bit will clear when you perform a successful shading value generation
procedure.
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