Camera Interface
2-10 BASLER L304kc
Draft
2.5.5 L304kc Video Data Output Modes
L304kc cameras can operate in 3 tap 8 bit, 2 tap 10 bit and 2 tap 8 bit output modes. (See Section
3.2 for more information about setting the camera for a particular output mode.)
Operation in 3 Tap 8 Bit Output Mode
In 3 tap 8 bit output mode, L304kc cameras operate with a 30 MHz pixel clock. On each clock
cycle, the camera transmits 8 bits of data for a red pixel, 8 bits of data for a green pixel, 8 bits of
data for a blue pixel, a line valid bit and a data valid bit. The assignment of the bits is as shown in
Tab l e 2-3.
The Camera Link pixel clock is used to time data sampling and transmission. As shown in Figures
2-4 and 2-5, the camera samples and transmits data on each rising edge of the pixel clock. The
line valid bit indicates that a valid line is being transmitted and the data valid bit indicates that valid
pixel data is being transmitted. Pixel data is only valid when the line valid and data valid bits are
both high.
Video Data Sequence
When the camera is not transmitting valid data, the line valid and data valid bits transmitted on
each cycle of the pixel clock will be low. Once the camera has completed line acquisition, it will
begin to send valid data:
• On the clock cycle where pixel data transmission begins, the line valid and data valid bits will
become high. Eight of the bits transmitted during this clock cycle will contain the data for pixel
number one in the red line, eight bits will contain the data for pixel number one in the green
line and eight of the bits will contain the data for pixel number one in the blue line.
• On the second cycle of the pixel clock, the line valid and data valid bits will be high. Eight of
the bits transmitted during this clock cycle will contain the data for pixel number two in the red
line, eight bits will contain the data for pixel number two in the green line and eight of the bits
will contain the data for pixel number two in the blue line.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
4080 cycles.
1
)
• After all of the pixels have been transmitted, the line valid and data valid bits will become low
indicating that valid pixel data is no longer being transmitted.
Figure 2-4 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and Figure 2-5 shows the data sequence when the camera is operating
in programmable exposure mode.
____________________
1
When the AOI and Stamp features are used, the number of cycles could be more or less than
4080. See Sections 3.7 and 3.8 for more information.
L
The data sequence outlined below, along with Figures 2-4 and 2-5, describe what is
happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock) and on others, it must be
sampled on the falling edge. Also, some devices are available that allow you to se-
lect either rising edge or falling edge sampling. Please consult the data sheet for the
receiver you are using for specific timing information.
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