34
Z31980_00_03
Design and Function
5.3.1.1 Main Board
The Main Board contains the Pulse generation for two RF channels, the Receiver Chan-
nel including digital filtering and and Gradient Channel with LVDS Interface.
The Pulse Programmer is preloaded with a complete 1D- or 2D-Experiment. Once
started, the entire experiment is run from the FPGA without interaction from the CPU.
There is an external trigger that can be used to trigger individual scans.
The receiver uses a direct sampling technique to digitize and downconvert the RF sig-
nal. The FPGA contains a DSP core which performs the digital filtering down the final
required spectral bandwidth. The data from each single FID is stored in the FPGAs inter-
nal memory. Accumulation of FIDs is performed by the on board Arm CPU , which then
transfers the data to the front end whenever it is requested.
The main board has a fixed transmit but a variable receiver routing.
DDS2 is equivalent to FCU2 in the signal routing table and is dedicated to 1H.
Figure 5.8 DDS2
DDS1 is equivalent to FCU1 in the signal routing table and is dedicated to C13.
Figure 5.9 DDS1
The Main Board is also the Can-Bus Master for the shim Control and the GAB/2 Back-
To Next Page
Loading...
