Epson LQ-510 - Page 99

REV.-A
PRINCIPLES OF OPERATION
2.3.6.4 Gate Array E05A02 Operation in Printhead Drive Circuit
The E05A02 gate array includes circuitry to interface the CPU and the printhead. This general-purpose gate
array has special commands that lighten the load on the CPU when outputing printhead data.
The gate array consists mainly of an 8-bit x 3 =
24-bit data latch. The gate array has functions (commands)
for writing data to all 24 bits of the data latches efficiently. Because the CS terminal of this gate array is
activated by accessing address F004 hex. and F005 hex., the command output address and data output
address are determined as shown in Table 2-8.
Table 2-6. E05A02 Gate Array Functions
r
Address (Hex.)
Function
F004 Outputs a command:
Bit 7: Data latch writing sequence set-up
0: Ascending order
1: Descending order
F005
Bit 6: HPW valid/invalid setting
Bit 5: Counter resetting
Bit 4 to Bit 0: Optional
Latches data and increases the counter:
When latching data, the data is NANDed with the contents of the current latch and is pro-
tected against double writes (the same data cannot be output twice in succession).
Latching data into all the data latches is completed by latching three bytes, one at a time.
When HPW is valid as a command, the latched head data is inverted, then output while
HPW is LOW.
NOTE: When the HPW setting is invalid, HPW output is in the open-drain ON state, independent of the HPW
input. The drive pulse is input to the HPW terminal.
LQ-510
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