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IEI
®
Technology, Corp.
o PCI power management registers by MCH
MAC Specific
o Optimized transmit and receive queues
o IEEE 802.3x-compliant flow-control support with software-controllable
thresholds
o Caches up to 64 packet descriptors in a single burst
o Programmable host memory receive buffers (256 B to 16 KB) and
cache line size (16 B to 256 B)
o Wide, optimized internal data path architecture
o 40 KB configurable Transmit and Receive FIFO buffers
o Descriptor ring management hardware for transmit and receive
o Optimized descriptor fetching and writeback mechanisms
o Mechanism available for reducing interrupts generated by transmit
and receive operations
o Support for transmission and reception of packets up to 16 KB
PHY Specific
o Integrated for 10/100/1000 Mb/s full- and half-duplex operation
o IEEE 802.3ab Auto-Negotiation and PHY compliance and
compatibility
o State-of-the-art DSP architecture implements digital adaptive
equalization, echo and crosstalk cancellation
o PHY cable correction and diagnostics
o Automatic detection of cable lengths and MDI vs. MDI-X cable at all
speeds
Host Off-Loading
o Transmit and receive IP, TCP, and UDP checksum off-loading
capabilities
o Transmit TCP segmentation and advanced packed filtering
o IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for
up to 4096 VLAN tags
o Jumbo frame support up to 16 KB
o Intelligent Interrupt generation (multiple packets per interrupt)
Manageability
o On-chip SMBus 2.0 port
o ASF 1.0 and 2.0
o Compliance with PCI Power Management v1.1/ACPI v2.0
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