Intel
®
Server Board S2600CP and Server System P4000CP TPS Intel
®
Server System P4000CP Power System Options
Revision 1.1
Intel order number G26942-003
147
Figure 60. PSON# Required Signal Characteristic.
13.3.6.2 PWOK (Power OK) Output Signal
PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that power
supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. See Table
46 for a representation of the timing characteristics of PWOK. The start of the PWOK delay time
shall inhibited as long as any power supply output is in current limit.
Table 106. PWOK Signal Characteristics
Signal Type
Open collector/drain output from power supply. Pull-up to VSB
located in the power supply.
PWOK = High Power OK
PWOK = Low Power Not OK
MIN MAX
Logic level low voltage, Isink=400uA 0V 0.4V
Logic level high voltage, Isource=200
A
2.4V 3.46V
Sink current, PWOK = low 400uA
Source current, PWOK = high 2mA
PWOK delay: T
pwok_on
100ms 1000ms
PWOK rise and fall time
100
sec
Power down delay: T
pwok_off
1ms 200msec
A recommended implementation of the Power Ok circuits is shown below.
Note: the Power Ok circuits should be compatible with 5V pull up resistor (>10k) and 3.3V pull
up resistor (>6.8k).
1.0 V
PS is
enable
d
2.0 V
PS is
disable
d
1.0
V
2.0
Enabled
Disabled
0.3V ≤ Hysterisis ≤ 1.0V
In 1.0-2.0V input voltages range is
required
3.46V
0V
To Next Page
Loading...
Need help?
General
