Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture
Revision 1.8 17
Intel Order Number: E14960-009
o Interface to ICH9R South Bridge
o 100 MHz reference clock shared with PCI Express* interface(s)
PCI Express* x8 Interface
o Connected to two PCI Express* X8 connectors as shown in the block diagram
o Compliant with the PCI Express* base specification
The MCH accepts access requests from the host (processor) bus and directs those accesses to
memory or to one of the PCI Express* or PCI buses. The MCH monitors the host bus,
examining addresses for each request. Accesses may be directed to the following queues:
A memory request queue for subsequent forwarding to the memory subsystem
An outbound request queue for subsequent forwarding to one of the PCI Express* or
PCI buses
The MCH also accepts inbound requests from the Intel
®
ICH9R. The MCH is responsible for
generating the appropriate controls to control data transfer to and from memory.
The MCH is a FC-BGA device and uses the proven components of the following previous
generations:
Hub interface unit
PCI Express* interface unit
DDR2 memory interface unit
The MCH incorporates an integrated PCI Express* interface. The PCI Express* interface allows
the MCH to directly interface with the PCI Express* devices. The MCH also increases the main
memory interface bandwidth and maximum memory configuration with a 72-bit wide memory
interface.
The MCH integrates the following main functions:
An integrated high performance main memory subsystem
A PCI Express* bus which provides an interface to the PCI Express* devices (Fully
compliant to the PCI Express* Base Specification, Rev 1.0a)
A DMI which provides an interface to the Intel
®
ICH9R
Other features provided by the MCH include the following:
Full support of ECC on the processor bus
Twelve deep in-order queue, two deep defer queue
Full support of unbuffered DDR2 ECC DIMMs
Support for 512 MB, 1 GB, and 2 GB DDR2 memory modules
3.2.1.1 Segment F PCI Express* x8
The MCH PCI Express* Lanes 0~7 provide an x8 PCI Express* connection directly to the MCH.
This resource can support x1, x4, and x 8 PCI Express* add-in cards or cards through the I/O
riser when using the riser slot for the L board SKU.
Table 4. Segment F Connections
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