Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture
Revision 1.8 19
Intel Order Number: E14960-009
Supports ECC or non-ECC DIMMs.
Different memory technologies (size and density) can be used.
Single Channel Mode (either channel can be used): DIMM slots (within the same
channel) may be populated in any order.
Dual Channel Interleaved Mode: DIMM slots can be populated in any order as long as
the total memory in each channel is the same.
Dual Channel Asymmetric Mode: DIMM slots may be populated in any order.
3.2.2 PCI-X Hub (LX board SKU only)
The PCI-X Hub (PXH-V) is a peripheral chip that performs PCI/PCI-X bridging functions
between the PCI Express* interface and the PCI/PCI-X bus. The PXH-V contains two PCI bus
interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X
mode (66,100, or 133 MHz), for either 32 or 64 bits.
3.2.2.1 Segment E 64bit/133MHz PCI-X Subsystem
One 64-bit PCI-X
bus segment is directed through the PXH-V. This PCI-X segment (segment E)
provides the following:
o Two 3.3 V 64-bit PCI-X slots
On Segment E, PCI-X is capable of speeds up to 133 MHz operation and supports full-length
PCI and PCI-X adapters.
3.2.2.1.1 Device IDs (IDSEL)
Each device under the PCI-X
hub bridge has an IDSEL signal connected to one bit of AD
[31:16], which acts as a chip select on the PCI-X bus segment in configuration cycles. This
determines a unique PCI-X device ID value for use in configuration cycles. The following table
shows the bit to which each IDSEL signal is attached for P64-C devices and a corresponding
device description.
Table 6. Segment E Configuration IDs
IDSEL Value Device
18 PCI-X Slot 1 (64-bit/66-133 MHz) (LX board SKU only)
17 PCI-X Slot 2 (64-bit/66-133 MHz) (LX board SKU only)
3.2.2.1.2 Segment E Arbitration
The PX
H-V supports two PCI masters: two PCI-X slots or one riser slot. All PCI masters must
arbitrate for PCI access using resources supplied by the PXH-V. The host bridge PCI interface
(PXH-V) arbitration lines REQx* and GNTx* are a special case because they are internal to the
host bridge. Table 7 defines the arbitration connections.
Table 7. Segment D Arbitration Connections
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